1. Field of the Invention
The present invention relates to a synchronization circuit. More particularly, the invention relates to a high speed synchronization circuit in a semiconductor integrated circuit.
2. Description of the Related Art
In a synchronization circuit operative in synchronism with a clock signal, a circuit design based on the clock signal and a D-type flip-flop (DFF) has been currently employed, frequently. There are some synchronization circuit, in which a plurality of circuit structures, each disposing a predetermined logic circuit between DFFs operative in synchronism with the clock signal, are connected in cascade connection. In such case, the DFF serves as a latching circuit which latches an input signal from the logic circuit in the preceding stage in synchronism with the clock signal and feeds the latch signal to the logic circuit in the later stage in synchronism with the clock. Supply of the clock signal to these DFFs is performed by supplying a common clock signal through a clock tree.
An example of a known structure of the DFF to be employed in the synchronization circuit of the type set forth above as the latching circuit is shown in FIG. 7. In FIG. 7, an input signal from an input terminal IN is lead to an output terminal OUT through a transfer gate 73, an inverter 74, a transfer gate 77 and an inverter 78 in sequential order . An output of the inverter 74 is fed back to an input of the inverter 74 via an inverter 75 and a transfer gate 76.
On the other hand, an output of the inverter 78 is fed back to an input of the inverter 78 via an inverter 79 and a transfer gate 80. A clock signal from a clock input terminal CLK performs ON/OFF control of respective transfer gates 73,76, 77 and 80.
In the DFF constructed as set forth above, considering a period, in which the input data should not vary before a rise-up timing of the clock signal, namely a set up period T.sub.su, a period, in which the input data should not vary after rising up of the clock signal, namely a hold period T.sub.hold, a period, in which an output data varies after rising up of the clock signal, namely a delay period T.sub.pd, the following definition can be established with reference to FIG. 7.
The set up period T.sub.su is defined by a difference between a period required for closing the transfer gate 73 in response to variation of the clock signal and a period, in which an input signal of the input terminal IN varies and the signal reaches a node A6. The hold period T.sub.hold is defined by a period required for closing the transfer gate 73 in response to variation of the clock signal. The delay period T.sub.pd is defined a period, in which the transfer gate 77 is opened in response to variation of the clock signal and the signal of the node A4 is propagated to the output terminal OUT.
Now, a minimum value of an input/output delay period required in the logic circuit is considered. Namely, condition that when the clock signal is risen, the output data of the logic circuit receiving the input data upon rising of the immediately preceding clock signal, can be input to the logic circuit in the next stage, is considered. In other words, a condition that upon rising of the clock signal, the output data of the DFF simultaneously does not pass more than one logic circuits to be output data of other DFFs, is considered.
On the other hand, a maximum value of the input/output delay period required in the logic circuit is considered. Namely, a condition that, upon rising of the clock signal, the DFF outputs data, and the output of the DFF passes through the logic circuit to be an output data of the DFF upon rising of the next clock signal, is considered. The input/output delay period to the logic circuit employed in the synchronization circuit includes both of the minimum value and the maximum value.
Assuming that a period of the clock signal is T.sub.cyc, the maximum value of the input/output delay period of the logic circuit disposed between the DFFs becomes a period subtracted the set up period T.sub.su, the hold period T.sub.hold, the delay period T.sub.pd, a skew of the clock signal and its jitter from the clock period T.sub.cyc. On the other hand, the minimum value of the input/output delay period of the logic circuit to be disposed between the DFFs is a period subtracted the delay period T.sub.pd from a sum of the hold period T.sub.hold and the skew of the clock signal.
For example, in case of a circuit produced by typical 0.35 .mu.m CMOS process, the set up period T.sub.su is 150 ps, the hold period T.sub.hold is 150 ps, the delay period T.sub.pd is 200 ps, the skew of the clock signal is 150 ps and the jitter thereof is about 150 ps.
Now, when the period T.sub.cyc of the clock is assumed to be 10 ns (100 MHz), the maximum value of the input/output delay period of the logic circuit to be disposed between the DFFs becomes 9.2 ns, and similarly, the minimum value becomes 100 ps. Similarly, assuming that the period T.sub.cyc of the clock signal is 1 ns (1 GHz), the maximum value of the input/output delay period of the logic circuit to be disposed between the DFFs becomes 200 ps and, similarly, the minimum value becomes 100 ps.
In general, due to a fluctuation of the diffusion condition of the device, namely due to the fluctuation of the channel length or the oxide layer of the transistor, fluctuation of a temperature or a power source voltage, the input/output delay period of the logic circuit may fluctuate. For example, assuming that the minimum value is one, the maximum value is varied to be about two.
Namely, when the period of the clock signal is assumed to be 1 ns (1 GHz), it becomes quite difficult to set the input/output delay period of the logic circuit between 100 ps to 200 ps. For setting the input/output delay period of the logic circuit between 100 ps to 200 ps, it becomes necessary to use less fluctuation of the diffusion condition of the device by lowering yield in manufacturing and to use temperature control or high precision power source so as not to cause fluctuation of the temperature or the power source voltage, to be a factor of cost-up.
On the other hand, due to timing error of the clock supplied to individual DFF within LSI due to increasing of number of elements or increasing of area of the LSI, the skew of the clock is inherently increased. When the skew of the clock is caused, it becomes difficult to satisfy the hold period of the DFF to cause a necessity to add large number of delay elements between the DFFs to design the circuit for avoiding a signal path having a delay period less than a predetermined minimum delay period. In this case, number of delay elements of the overall LSI becomes huge to cause increasing of the chip area and increasing of power consumption. On the other hand, when the delay element is not added, malfunction of the LSI can be caused.
As a method for solving the foregoing problem, there is a method disclosed in Japanese Unexamined Patent Publication No. Heisei 7-249967, for example. FIG. 8 shows a construction disclosed in the above-identified publication. In FIG. 8, the input signal of the input terminal IN is lead from the output terminal OUT through a transfer gate 88, an inverter 89, a transfer gate 90, an inverter 91, an inverter 92, a transfer gate 94 and an inverter 95 in sequential order. On the other hand, an output of the inverter 92 is fed back to an input to the inverter 91 via a transfer gate 93.
The clock signal CLK is delayed for a given period by an inverter 81 and buffers 82 and 83 and becomes one input of an NAND gate 84. To the other input of the NAND gate 84, the clock signal is directly supplied. The output of the NAND gate 84 is used for ON/OFF control of the transfer gates 88, 90, 93 and 94 via the inverters 85, 86 and 87.
At rising of a pulse signal generated at a node B3 upon rising of the clock signal, an input data is taken from the input terminal IN. At falling down of the pulse signal, the taken input data is lead to the output terminal OUT.
The set up period T.sub.su of this circuit is defined by a difference between a period of closing of the transfer gate 88 in response to the clock signal and a period, in which an input signal of the input terminal IN varies and the signal reachs a node B1. The hold period T.sub.hold is defined by a period to close the transfer gate 88 in response to variation of the clock signal. The delay period T.sub.pd is defined to a period to propagate a signal of a node B2 by opening the transfer gate 94 in response to variation of the clock signal, to the output terminal OUT.
Next, similarly to the prior art shown in FIG. 7, the minimum value and the maximum value of the input/output period of the logic circuit is derived. The maximum value of the input/output delay period of the logic circuit becomes period subtracted the set up period T.sub.su, the hold period T.sub.hold, the delay period T.sub.pd, a width T.sub.pw of a pulse B3, the skew of the clock and the jitter thereof from the clock period T.sub.cyc. On the other hand, the minimum value becomes a period subtracted the delay period T.sub.pd from the hold period T.sub.hold by setting the pulse width T.sub.pw greater than the clock skew.
Namely, in the synchronization circuit employing the prior art shown in FIG. 8, malfunction of the LSI due to clock skew caused by timing error of clock distribution or so forth can be avoided.
However, it is still not possible to make the minimum value of the input/output delay period required to the logic circuit zero. On the other hand, even if the pulse width T.sub.pw and the clock skew are the same, the maximum value of the input/output delay period of the logic circuit cannot be made smaller than the circuit using the prior art shown in FIG. 7.
On the other hand, as a further prior art, there is a synchronization circuit constructed as shown in FIG. 9. This prior are has been disclosed in 1996, IEEE, International Solid State Circuits Digest of Technical Papers, pp 138 to 139.
Referring to FIG. 9, an input signal from the input terminal IN is supplied to respective gates of an NMOS transistor (hereinafter simply referred to with omitting transistor) 101 and a PMOS 103. Between power sources, PMOS 99, NMOSs 100, 101 and 102 are connected in series in sequential order. The PMOS 103 is disposed between a drain of the NMOS 100 and a reference potential. On the other hand, a PMOS 105 and NMOSs 106 to 108 are connected between the power sources in series in sequential order. Also, a PMOS 104 is connected between a gate of the PMOS 105 and the reference potential. The gate of the PMOS 105 and the drain of the NMOS 100 are connected in common.
To a drain of the NMOS 106, a pair of inverters 109 and 110 are provided in positive feedback structure to operate as an output amplifier. An output of the output amplifier serves as the output terminal OUT.
The clock signal CLK is directly supplied to respective gates of the PMOS 99 and NMOSs 100 and 106. On the other hand, the clock signal CLK is supplied to gates of the NMOS 102, PMOS 104 and NMOS 108 via a series circuit of the inverters 96 to 98.
In this circuit, the data on the input terminal IN is lead to the output terminal OUT as is for a period (pulse width T.sub.pw) propagating the clock signal of a node IT1 from a timing of rising of the clock signal. In other period, the signal level of the output terminal OUT is maintained.
A period where the input data should not vary before rising timing of the clock signal, namely the set up period T.sub.su is set to zero, a period, in which the input data should not vary after rising up of the clock signal, namely a hold period T.sub.hold is zero and a period, in which an output data varies after rising up of the clock signal, namely a delay period T.sub.pd is defined by a period to propagate the signal of a node IT2 to the output terminal OUT in response to variation of the clock CLK.
Next, similarly to the former prior art, the maximum value and the minimum value of the input/output delay period of the logic circuit is derived. The maximum value becomes a value subtracted the delay period T.sub.pd from the period Y.sub.cyc of the clock signal. However, the minimum value of the input/output delay period required to the logic circuit becomes a period subtracted the delay period from a sum of the pulse width T.sub.pw of the pulse signal and the skew of the clock signal.
Namely, in the prior art employing the third circuit, the maximum value of the input/output delay period of the logic circuit can be set so as not to be influenced by the clock skew, jitter, the set up period present in the first and second prior art or the hold period. However, malfunction of the LSI due to clock skew caused by timing error of the clock distribution or so forth, cannot be prevented. On the other hand, as set out in the first prior art, delay element becomes necessary for preventing malfunction to make it difficult to increase power consumption and to cause difficulty in designing and verification of operation in the high speed circuit.
As set forth above, as a construction where the circuits provided with the desired logic circuit between the DFFs are connected in cascade connection, in the synchronization circuit operative in synchronism with the clock signal, influence of the skew of the clock signal and jitter thereof cannot be ignored. Also, the synchronization circuit should be influenced by fluctuation of the temperature or so forth during manufacturing of the device, fluctuation of the channel length or gate oxide layer, fluctuation of the temperature during operation or fluctuation of the power source voltage.